1.1.1
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Control unit
Controls and coordinates all activities of the CPU. Directs flow of data between CPU and other devices.
Arithmetic logic unit (ALU)
Carries out arithmetic and logic calculations. Arithmetic operations are on fixed and floating point numbers: ADD/ SUBTRACT/ MULTIPLY / DIVIDE Boolean logic operations: Comparison /AND /OR/ NOT/ XOR Often uses general purpose registers to temporarily hold results of calculations such as accumulator.
Registers
Are small storage locations used to hold data temporarily. They have high read and write speeds.
Program counter (PC)
Stores the address of the next instruction. Has a very close relationship to MAR, at the start of every fetch, decode, execute cycle address held in PC is stored in MAR.
Memory address register (MAR)
Temporarily holds the address of the memory location which needs to be fetched or set from main memory that the processor needs to access.
Memory data register (MDR)
Used to temporarily store data which is read from/ written to memory. Sometimes known as buffer register (MBR) All data to and form memory must travel down data bus and pass through MDR.
Current instruction register (CIR)
Area where the current instruction is being carried out. The operation is divided into operand and opcode.
Accumulator
Stores the results of the calculations made by the ALU.
Interrupt register
Generates and detects interrupts.
Assembly code
Uses mnemonics to present instructions, for instance SUB represents subtraction. This is a simplified way of representing machine code, easier to remember than binary.
Assembly code mnemonics
Simplified
Buses
Communication paths between the CPU, memory and other components.
Address bus
A one directional bus that transmits memory addresses that are used as operands in programming instructions, so that data can be retrieved from main memory.
Data bus
A bi-directional path for moving data and instructions between system components.
Control bus
A bi-directional bus to transmit command, timing and specific status information between system components
Control bus
A bi-directional bus to transmit command, timing and specific status information between system components.
Fetch decode execute (FDE)
PC MAR Address Bus Memory Data bus MDR CIR Decode Uni
Fetch
• The address of the next instruction is copied from the PC to the MAR • The fetch signal is sent across the control bus. The content of the MAR are transferred across the address bus. • The contents of the memory location stored in the MAR are sent across the data bus and stored in the CIR • the PC increments by 1
Decode
• The contents of the CIR are sent to the CU and divided. The Opcode tells you the instruction to be carried out and the operand stores the address of any data which might be needed. • The operand is sent to the MAR and the data is fetched from memory and stored in the MDR
Execute
The appropriate opcode is carried out on the operand.
How does a program branch happen and what is the result?
Due to an if statement, function, procedure call or loop. Results are that the next instruction held in the PC is not carried out.
Clock speed
Indicates the number of instructions the CPU can process per second, unit is hertz. The clock speed is determined by the system clock. This is an electronic device which generates signals, switching between 0 and 1.
Advantages and disadvantages of increasing clock speed
you can carry out more instructions in a given time; improved performance more heat generated meaning computers must be cooled (either with heat sync/fan or water/oil cooling)
Multiple cores
A core is an independent processor, which is able to compile its own fetch-execute cycle. The more cores a computer has, the more fetch-execute cycle it can carry out at any given time. Dual-core processor has two processors linked together in the same integrated circuit. Quad-core computer has four linked processors (each with its own registers, ALU, accumulator and control unit)