1.1.1 Structure and function of the processor
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Describe the ALU
The Arithmetic Logic Unit carries out mathematical operations and logical calculations.
Describe the CU
Coordinates the activities of the CPU and decodes instructions
Describe the PC register
Holds the address of the next instruction to be executed. Is incremented by one on every cycle.
Describe the ACC register
Stores the results of ALU calculations. Holds all input/output. Stores data which has come from the MDR/RAM.
Describe the MAR
Holds the address of the memory location that is to be read from or written to
Describe the MDR
Temporarily stores data that has been read or that needs to be written to memory
Describe the CIR
Holds the current instruction being executed. This includes the opcode (a value that specifies the operation to be performed) and operand (the object of a mathematical operation).
Describe the data bus
A bi-directional bus used for transporting data and instructions between components.
Describe the address bus
A uni-directional bus used to transmit memory addresses from the CPU to the RAM.
Describe the control bus
A bi-directional bus used to transmit control signals from the control unit between components.
Describe the fetch stage of the FDE cycle
The contents of the PC are sent to the MAR. The address is transferred along the address bus to main memory. The control unit transfers a read signal along the control bus. Contents stored in the memory address are transferred along the data bus. Contents from memory are stored in the MDR and sent to the CIR. The PC is incremented.
Describe the decode stage of the FDE cycle
The instruction held in the CIR is decoded by the decode unit.
Describe the execute stage of the FDE cycle
The instruction held in the CIR is executed. Results of processing by the ALU (if it occurs) are stored in the accumulator.
How does clock speed affect the performance of the CPU?
Clock speed refers to the number of cycles per second and is the speed at which the FDE cycle is completed. If the clock speed is faster, more cycles can be completed per second so more instructions can be executed per second so the program takes less time to run.
How does the number of cores affect the performance of the CPU?
The greater the number of cores a processor has the greater the number of FDE cycles that can be conducted simultaneously. Therefore, more data instructions are executed at one time, increasing the performance of the CPU
How does the size of the cache affect the performance of the CPU?
The cache stores memory that contains recently, frequently used instructions. This memory has a faster read/write speed than RAM and is closer to the CPU. A larger cache enables there to be more space for data in its memory. This means that RAM needs to be accessed less frequently and the CPU performance is increased as accessing cache is quicker than accessing RAM.
What are the reasons why doubling the number of cores doesn’t double the speed of the CPU?
• Some instructions may not be able to be run in parallel • An instruction may take longer than usual to execute because its waiting for another instruction to be completed • Clockspeed / cache / bottlenecks may be effecting the speed of the processor • Programs need to be written to specifically use multiple cores
Explain how pipelining improves the performance of a CPU
It enables the concurrent processing of multiple instructions. This allows the next instruction to be fetched whilst another is being decoded and another executed. The output of one instruction is the input to the next. This increases the number of instructions processed in a set period of time and prevents idle components. It’s only possible on the Harvard architecture.
Describe the Von Neumann Architecture
The Von Neumann architecture uses one physical piece of memory for both data and instructions. It uses one data and one address bus. It can only read/write data or instructions, not both at the same time. Its’s fairly uncomplex and cheap. It allows for dynamic allocation between instruction and data. It’s usually used for general purpose computers.
Describe the Harvard Architecture
It uses separate memory for data and instructions. This means that you could run out of memory in one area with unused memory in the other area. It uses separate data and address buses for each piece of memory, leading to its complex design. It can read/write data and instructions simultaneously. This enables faster processing. The development of it is expensive due to the requirement for CPU pins and a complex motherboard. It is used in devices which prioritise high performance speed and efficiency over a variety of uses, such as embedded systems.
Describe the contemporary architecture
Contemporary processing uses a combination of Harvard and Von Neumann architecture. Von Neumann when working with data and instructions in main memory. Harvard to divide the cache into instruction and data cache. It may includes features such as pipelining, cache memory, multiple cores, onboard graphics or performance boosting mode.