1.1.1 Structure Of The Processor
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ALU
The ALU performs arithmetic and logical operations on the data
Control unit
The control unit controls and coordinates the activities of the CPU, directing the flow of data between the CPU and other devices
Register
Tiny areas of extremely fast memory, located in the CPU, normally designed for a specific purpose
PC (Program Counter)
A register in the control unit that holds the address of the next instruction to be executed
ACC (Accumulator)
A general purpose register that is used to hold the results of operations carried out in the ALU
MAR (Memory address register)
A register in the CPU that stores the address of the memory location currently in use.
MDR (Memory data register)
A register in the CPU that is used to temporarily store the data read from or written to memory.
CIR (Current instruction register)
A register in the control unit that stores the current instruction being executed, divided into operand and opcode
Busses
A bus is a set of parallel wires connecting two or more components of a computer. Typically consists of 8, 16, 32 or 64 lines
Data bus
A bi-directional bus, transports data and instructions to and from system components
Address bus
Used to transmit the memory addresses specifying where data is to be sent to or retrieved from
Control bus
Carries control and command signals to and from component of a computer
Fetch-Decode-Execute
The complete process of retrieving an instruction from store, decoding it and carrying it out
CPU (Central processing unit)
The main part of the computer consisting of the registers, ALU and control unit
Clock speed
The number of clock cycles completed per second. The higher the clock speed the faster the computer may work
Core
A core is a complete processing unit within the CPU
Cache
A small, but extremely fast type of RAM, located in the CPU chip
Pipelining
Concurrently completing the fetch-decode-execute cycle of 3 separate instructions
Von Neumann Architecture
Traditional computer architecture that has a shared memory and data bus used for both data and instructions
Harvard architecture
A computer architecture with physically separate memories for instructions and data
Contemporary architecture
Processing that uses Von Neumann architecture for main memory and Harvard architecture for cache, divided into instruction and data cache