Unit 1: Computer Components

• Coordinates the activity of all other processor components • Manages the phases of the Fetch-Execute cycle • Decodes instructions received into the processor

• Program Counter (PC) • Memory address register (MAR) • Memory data register (MDR) • Current instruction register (CIR) • Accumulator (ACC)

• Holds the address if the next instruction • Incremented by one when the instruction is read, ready for the next cycle.

• Contains the address of the memory location from which data or an instruction is to be fetched.

• Temporarily stores the data being transferred to and from memory. • It acts as a buffer, allowing the processor and memory units to act independently without being affected by minor differences in operation.

Holds the instruction currently being decoded or executed.

Holds the result of an instruction.

Used to carry out instructions received by the processor and produce the processed output.

A continuously cycling signal that is used as a timing pulse for all processor components.

Buses are a set of ​parallel wires​ which connect ​two or more components​ inside the CPU.

The system bus consists of three separate buses carrying control signals, addresses and data

Registers are ​small memory cells​ that operate at a ​very high speed​. They are used to temporarily store data​ and all ​arithmetic​, ​logical​ and ​shift​ operations occur in these registers.

This is a ​bi-directional bus​ used for transporting ​data​ and ​instructions​ between components.

Used to transmit the ​memory addresses​ specifying where data is to be sent to or retrieved from. The width of the address bus is proportional to the ​number of addressable memory locations​.

This is a ​bi-directional​ bus used to transmit ​control signals​ between internal and external components. The control bus coordinates the use of the address and data buses and provides status information between system components.

• Bus requests • Bus grant • Memory write • Memory read • Interrupt request • Clock

Assembly code​ uses ​mnemonics​ to represent instructions; the instruction is divided into ​operand​ and ​opcode​ in the Current Instruction Register. The operand contains the data or the ​address​ of the data upon which the operation is to be performed. The opcode specifies the ​type of instruction​ to be executed.

Pipelining is the process of completing the fetch, decode, and execute cycles of ​three separate instructions​ ​simultaneously​, holding appropriate data in a ​buffer​ in close proximity to the CPU until it’s required. While one instruction is being executed, another can be decoded and another fetched.

Pipelining is aimed to reduce the amount of the CPU which is kept ​idle​. It is separated into instruction pipelining​ and ​arithmetic pipelining​.

Instruction pipelining is separating out the instruction into fetching, decoding, and executing.

Arithmetic pipelining is breaking down the arithmetic operations and overlapping them as they are performed.

Fetch phase: - Address from the PC is copied to the MAR - Instruction held at that address is copied to MDR by the data bus - Simultaneously, the contents of the PC are increased by 1 - The value held in the MDR is copied to the CIR Decode phase: - The contents of CIR are split into operand and opcode Execute phase: - The decoded instruction is executed

Clock speed, number of cores and the amount and type of cache memory.

All processor activities begin on a clock pulse, and the clock speed is the time taken for one clock cycle to complete. Consequently, the higher a system’s clock speed, the more instructions it can process over a given time.