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1: The CPU

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卡片总数: 24内容版本: v4公开卡包更新时间: 8/1/2026

卡片预览 (24 张)

#1
正面 (问题)

CU

背面 (解答)

• Coordinates all activities of the CPU • Directs the flow of data between the CPU and other devices • FDE cycle happens here • Sends memory read/write signals to main memory on the control bus

#2
正面 (问题)

PC

背面 (解答)

• Holds the address of the next instruction to be executed • Holds a close relationship with MAR: the address held in the PC is copied to the MAR

#3
正面 (问题)

MAR

背面 (解答)

-Holds the address of the memory location from which data is to be fetched or to which data is to be written -Sends addressed to memory down address bus

#4
正面 (问题)

MDR

背面 (解答)

• Temporarily stores the data which has been read from or written to memory • All data to and from memory must pass through the MDR via the data bus.

#5
正面 (问题)

CIR

背面 (解答)

• Holds the current instruction being executed • Contents of MDR are copied into CIR if it is an instruction • Contains opcode and operands of the current instruction • Instruction = opcode + operands

#6
正面 (问题)

ALU

背面 (解答)

-performs arithmetic and logic functions in the CPU -ADD, SUBTRACT, MULTIPLY, DIVIDE - AND, OR, NOT, XOR - Binary shift -Comparison

#7
正面 (问题)

ACC

背面 (解答)

• a general purpose register which stores results of calculations performed in the ALU as well as control information • The more general purpose registers a CPU has, the faster it may operate

#8
正面 (问题)

Address Bus

背面 (解答)

Carries memory addresses that identify where the data is being read or written to

#9
正面 (问题)

Data Bus

背面 (解答)

Carries the binary that make up the actual information being transmitted around the CPU

#10
正面 (问题)

features of Von Neumann architecture

背面 (解答)

• Shared memory space for instructions and data • Instructions and data are stored in the same format • A single control unit or processor follows a linear FDE cycle • One instruction at a time • Registers are used as fast access to instructions and data

#11
正面 (问题)

Features of Harvard architecture

背面 (解答)

• Instructions and data stored in separate memory units • each has its own bus • Reading and writing data can be done at the same time as fetching an instruction • Used by RISC processors

#12
正面 (问题)

How do Von Neumann and Harvard architectures differ from contemporary architectures?

背面 (解答)

• SIMD (Single Instruction Multiple Data): Parallel processing is where a processor carries out a single instruction on multiple data items at the same time - often used by graphic processors • MIMD (Multiple Instructions Multiple Data), another version where multiple instructions are carried on multiple data items across several cores • Distributed computing : Where multiple computers on a shared network each take part on part of a bigger problem

#13
正面 (问题)

Clock Speed

背面 (解答)

• measured in hertz (Hz) • Number of FDE cycles per second

#14
正面 (问题)

Cache size

背面 (解答)

• Temporary storage of frequently used data and instructions being read to and written from • Located on or near the CPU • Stores copies of recent data and instructions • Quicker to access than RAM, improving efficiency of CPU

#15
正面 (问题)

Number of cores

背面 (解答)

• A core is a complete copy of the CPU, with its own separate registers and units • CPUs with multiple cores have more power to run multiple programs at the same time

#16
正面 (问题)

What are registers?

背面 (解答)

Small memory cells that operate at very high speeds and used to temporarily store data involved in the FDE cycle.

#17
正面 (问题)

Fetch

背面 (解答)

• Address from the PC is copied to the MAR • Instructions held at that address is copied to the MDR by the data bus • simultaneously the PC is incremented • The value held in the MDR is copied to the CIR

#18
正面 (问题)

Decode

背面 (解答)

• The contents of CIR are split into opcode and operand

#19
正面 (问题)

Execute

背面 (解答)

-The opcode is executed on the operand.

#20
正面 (问题)

ADD

背面 (解答)

add

#21
正面 (问题)

SUB

背面 (解答)

subtract

#22
正面 (问题)

STA

背面 (解答)

store

#23
正面 (问题)

LDA

背面 (解答)

load

#24
正面 (问题)

BRA

背面 (解答)

Branch Always