7.3 Fetch-Decode-Execute Cycle
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Describe the role of the control unit
To control operation of fetch-execute cycle; Controls fetching / loading / storing operations; Determines the type of an instruction; A. decodes instructions To execute (some) instructions; To synchronise operation of processor; To send control signals / commands to other components; To control the transfer of data between registers; To handle interrupts;
Describe the role of the arithmetic and logic unit
Performs arithmetic and logical operations e.g. binary addition, AND, OR
What is a register?
Fast-access, temporary memory location inside the processor
What does the Program Counter store?
The ADDRESS of the NEXT instruction to be fetched
What does the memory address register store?
The ADDRESS of the CURRENT instruction being fetched
What does the memory buffer register store?
The data item currently being accessed
What does the accumulator store?
Intermediate results of operations performed by the ALU
What is the role of the status register?
Stores information about the result of the last instruction. Stores bits/flags which affect the operation of the control unit.
State what happens during the fetch stage of the Fetch-Execute cycle. Include information about buses.
The contents of PC are copied to MAR. Address bus used to transfer this address to main memory Read signal sent along control bus PC increments by 1. Contents of addressed memory transferred to MBR via data bus. Contents of MBR copied to CIR.
State what happens during the decode stage of the Fetch-Execute cycle [3]
Instruction to decode is held in CIR and decoded by the control unit Instruction split into opcode and operand
State what happens during the execute stage of the Fetch-Execute cycle [4]
If necessary, data is fetched. Opcode identifies the type of operation to be performed. Operation performed by the control unit. Control bus transfers signals to other components to initiate actions. ALU used for calculations/comparisons. Result stored in accumulator. If jump/branch required PC is updated. Status register is updated.
State two examples of when the status register might have a bit set
Arithmetic results including: Overflow/underflow/positive/negative/zero/carry; Interrupts;
Describe four steps that a processor goes through during the fetch stage of the Fetch-Execute cycle. You must explain the purpose of each step.
Step 1: Description Contents of the Program Counter / PC transferred to the Memory Address Register / MAR Explanation so that the PC can be updated // to enable the memory address to be transferred along the address bus/to the memory Step 2: Description Contents of MAR placed onto address bus Explanation so the correct location in the main memory will be accessed Step 3: Description Contents of addressed memory location/value received on data bus loaded into the Memory Buffer Register / MBR Explanation not all fetches will be for instructions so cannot be loaded directly into Current Instruction Register / CIR // the value will only be present transiently on the bus so must be stored in a register // the MBR is used to cope with the speed difference between the processor and the main memory Step 4: Description (Contents of) PC is incremented Explanation so that the next instruction in the sequence can be fetched Step 5: Description The contents of the MBR is copied to the CIR Explanation so that if data is fetched/written during the execute phase it does not overwrite the instruction // because the control unit uses the instruction from the CIR
Explain the difference between dedicated and general purpose registers [2]
Dedicated: a register that has a specific purpose within the processor (e.g. program counter stores address of next instruction to be fetched) General-purpose: a register used for temporarily holding data. A programmer can choose what each general-purpose register is used for.