1.1 structure of the CPU

MAR MDR CIR Program counter accumulator

temporary small storage used for a specific purpose faster than RAM used in FDE cycle

the control unit decodes instructions sends signals to control movement of data uses control buses

address bus control bus data bus

sends the address of the address in the main memory

transmits control signals essentially tells the the CPU if data is being written to or read from memory

used by the CPU to locate the physical address in the MAR

busses consist of a series of connectors that transfer signals between internal components signals typically 16 32 64 bits

current instriction register if data sent to the MDR is an instruction and not data then copied over to the current instruction register

contains any number overflows

one control unit one bus for both instructions and data single processor (can have multiple cores) one instruction at a time program must be loaded into main memory to be executed instructions and data stored together

instructions and data in seperate memory locations two seperate buses for data and instructions can fetch instructions and data at the same time