CO1 WEEK 4 PARTS OF CPU

• Connected by busses • Tiny electronic switch • Can be turned of by applying voltage to their terminals • Arranging transistors in different ways = logic gates and circuits that preform operations • moore’s law=number of transistors double each year

Processors speed - clock speed =instructions per second - cpu requires fixed amount of clock cycles - Faster clock speed more instructions

-Control unit -ALU -Registers

Co ordinates the activity of all processor components - decided instruction’s received - manages the phases of FDE

carries out calculations and logic - includes eg +-x,divide -logic <> - Stored in Accumulator

• Small areas of volatile memory in cpu • temporary store for data • very fast • when data processed, values shifted in and out

PC -CIR -MAR -MDR -ACC

Stores the address of memory location that data is about to be written to or read from.

• Temporarily stores address of memory location of data Eg address of next instruction (copied from PC)

• Contains the contents of the memory address specified by MAR

stores the instruction that is currently being decoded or executed or copied from MDR - split into 2 first part is Operation code which decoded for CU the second part is data or address of data which sent to MAR

holds data while it’s being processed -stores all input/output as well as results of calculations

single control unit - linear - program and data stored together - same bus for data and instruction - FDE used - fetches data or instruction one at a time

Shared memory- can cause corruptions - memory leaks - bottle necks - Fetch rate

Units dif sizes better use of memory - different word lengths for dif units - Instructions more likely read only - multiple cores on one task

Physical space - complexity

Many instructions available = multiple cycles - complex design - more transistors = higher cost - less use of RAM - Variable n of bytes as instructions are longer

desktop, computer

limited instruction - once cycle - simple design - less transistors - less cost - heavy use of ram - Fixed num of bytes

Smartphones and tablets

Single instruction single data - pipeline - inside CPU

Single instruction Multiple data - array processing - graphics cards , game consoles

Multiple instruction Multiple Data - multicore - super computers - multicore chips

Staggers FDE cycle into 3 or more processing paths