1.1.1 Structure And Function Of The Processor

The CPU is responsible for processing all the data within the computer

The CPU consists of : ALU CU Registers: - PC - MDR - MAR - ACC - CIR

-Small fast memory cells used for (temporarily) storing data, within the processor. [1] -They have faster access speeds than RAM/secondary storage. [1]

Performs any arithmetical or logical operations. [1] E.g adding binary or using AND, OR, NOT

• Accepts the next instruction. • decodes instructions [1] • Sends control signals to coordinate the movement of data through the processor [1]

• Holds the address of the next instruction to be executed. [1] • is incremented by 1 on every cycle [1] • contents of the PC can be changed by BRANCH/JUMP instructions

• temporarily Stores the result of calculations ( usually from the ALU ) [2] • holds all input/Output in processor [1] • used as a buffer [1] • checked for conditional branching [1]

• Hold the address of a location from which data/ instructions is to be fetched from of written to. [2] • holds the address of the instruction sent from the PC [2]

• Temporarily stores data/instructions that has been read or data that needs to be written. [1] • acts as a buffer [1]

Holds the current instruction being executed divided up into operand and opcode

Bits can be carried in both directions

• are a set of Parallel wires which connect 2 or more components inside the CPU. • there are 3 buses which connect the CPU with the main memory (RAM) : The Data bus , address bus and control bus • collectively known as the system bus

• Used to transmit memory addresses specifying where data is to be sent or retrieved from. • adding a wire to the address bus doubles the number of addressable locations .

• this is a bi directional bus • transmits control signals from the CU to other parts of the processor (to allow synchronisation of signals to the rest of the processor) [1] • control signals include: Bus grants Bus requests Memory write Memory read Interrupt requests Clock

• Assembly code uses mnemonics to represent instrucions e.g ADD represents addition • it is a simplified way of representing machine code • the instruction is divided up into operand and opcode

• is used to determine the type of instruction and what hardware to use to execute it • is part of the instruction and indicates what to do and also contains the addressing mode

• is the address of where the operation is performed

The sequence of operations that are completed in order to execute an instruction

• PC is checked (as it holds the address of the next instruction to be executed ) [1] • Address from the PC is copied to the MAR [1] • The address is sent along the address bus to main memory [1] • CU sends a read signal down the control bus to main memory [1] • Instructions stored at that address is sent down the data bus to the MDR [1] • Instructions held in the MDR is copied to the CIR [1] • Contents of the PC are incremented by 1 [1]

• the CU decodes the instruction • The contents of the CIR are split into operand and opcode

• operand is sent to/ stored in the MAR • the address (operand) is sent down the address bus to main memory • CU send a read signal down the control bus to the main memory • contents stored at that address is sent down the data bus and stored in the MDR • contents of the MDR are copied to the ACC (Note: each line of LMC is one FDE cycle) - The opcode is executed on the operand

• Clock speed • Number of cores • Cache

• the clock speed is the number of clock cycles completed in a seconds • the higher the clock speed, The more clock cycles per second [1] • so more instructions can be executed per second [1] • therefore the program takes less time to run [1]

• a core is an independent processor that is able to execute its own fetch-execute cycles • a computer with multiple cores can complete more than one fetch-execute cycle simultaneously ( parallel processing ) • however some task can’t be spilt between cores and therefore have more cores is no quicker than having one • some programs are not optimised for the use of multiple cores